concat-hardware-0.1.0.0: Circuit description (HDL) via compiling-to-categories
Safe HaskellSafe-Inferred
LanguageHaskell2010

ConCat.Hardware.Verilog

Description

Generate Verilog code from a circuit graph

Documentation

genVerilog :: (GenBuses a, GenBuses b) => String -> (a :> b) -> IO () Source #

runVerilog :: (GenBuses a, GenBuses b) => String -> (a :> b) -> IO () Source #